/**
  ******************************************************************************
  * @file    Libraries/Device/TS32Fx/TS32Fx_LL_Driver/inc/ts32fx_ll_adkey.h
  * @author  TOPSYS Application Team
  * @version V1.0.0
  * @date    02-11-2018
  * @brief   This file contains all the ADKEY LL firmware functions.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT 2018 TOPSYS</center></h2>
  *
  *
  *
  ******************************************************************************
  */ 
  
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TS32FX_LL_ADKEY_H
#define __TS32FX_LL_ADKEY_H

#ifdef __cplusplus
 extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "ts32fx.h"
#include "ts32fx_system.h"

/** @addtogroup TS32Fx_StdPeriph_Driver TS32Fx Driver
  * @{
  */
     
/** @addtogroup adkey_interface_gr ADKEY Driver
  * @ingroup  TS32Fx_StdPeriph_Driver
  * @{
  */ 

/** @addtogroup ADKEY_LL_Driver ADKEY LL Driver
  * @ingroup  adkey_interface_gr
  * @brief Mainly the driver part of the ADKEY module, which includes \b ADKEY \b Register 
  * \b Constants, \b ADKEY \b Exported \b Constants, \b ADKEY \b Exported \b Struct, \b ADKEY
  * \b Data \b transfers \b functions, \b ADKEY \b Initialization \b and \b ADKEY \b Configuration 
  * \b And \b Interrupt \b Handle \b function.
  * @{
  */

/* Exported types ------------------------------------------------------------*/

/* Exported constants --------------------------------------------------------*/

/** @defgroup ADKEY_LL_Register_Constants ADKEY LL Register Constants
  * @ingroup  ADKEY_LL_Driver
  * @brief    ADKEY LL register constant table definition
  *
  *
@verbatim   
  ===============================================================================
                                Register Constants
  ===============================================================================  
  
    Register Constants mainly encapsulates each bit in each group in the ADKEY 
    register. In the process of configuration, the macro definition can be directly 
    called to configure the ADKEY register, mainly for convenience. Understand the 
    configuration of the ADKEY.
    
@endverbatim
  *
  * @{
  */

/***** ADKEY_CFG Register *****/
/*! RW(reserved), reserved configuration
 */
#define LL_ADKEY_CFG_ADDA_SET(n)                               (((n)&0x7) << 23)

/*! RW, The interval time period between two consecutive samples (n*ADCCLK)
 */
#define LL_ADKEY_CFG_ADC_D2DCYC(n)                             (((n)&0xF) << 13)

/*! RW, ADC prescale
 * 0  : 2 prescaler , other : ( n + 1) prescaler
 */
#define LL_ADKEY_CFG_ADC_PSC(n)                                (((n)&0x3F) << 4)

/*! RW, ADC prescale mask
 */
#define LL_ADKEY_CFG_ADC_PSC_MASK                              (0x3FUL << 4)

/*! RW, ADC prescale set
 * 0  : 2 prescaler , other : ( n + 1) prescaler
 */
#define LL_ADKEY_CFG_ADC_PSC_SET(p_adc, n)                     (p_adc->CFG = LL_ADKEY_CFG_ADC_PSC(n)| (p_adc->CFG &( ~(LL_ADKEY_CFG_ADC_PSC_MASK))))

/*! RW, DAC1 (12 bit DAC) enable
 */
#define LL_ADKEY_CFG_DAC_EN                                    (1UL << 2)

/*! RW, A/D Converter enabled
 */
#define LL_ADKEY_CFG_ADC_EN                                    (1UL << 0)

/***** ADKEY_CR Register *****/
/*! RW, Hardware data correction enabled
 */
#define LL_ADKEY_CR_CAL_EN                                     (1UL << 28)

/*! WO, Software reset module internal state
 */
#define LL_ADKEY_CR_SW_RST(p_adc)                              ((p_adc->CR)|(1UL<<27))

/*! RW, Data expansion bit selection
 */
#define LL_ADKEY_CR_DATA_SIGN                                 (1UL << 26)

/*! RW, Overrun interrupt enable
 */
#define LL_ADKEY_CR_ADC_OVR_IE                                (1UL << 25)

/*! RW, Select ADIF trigger mode (It only works when it's scan mode)  
 * 0  : ADIF will be generated each time the sequence is completed  
 * 1  : ADIF will be generated at the end of the scan mode  
 */
#define LL_ADKEY_CR_ADC_EOCS                                  (1UL << 24)

/*! RW, External trigger shift sample
 * After the trigger signal is generated, the clock cycle with a delay of N PCLK starts sampling again  
 * 0: not delay  
 * 1: 4   cycles  
 * 2: 16  cycles  
 * 3: 32  cycles  
 * 4: 64  cycles  
 * 5: 128 cycles  
 * 6: 256 cycles  
 * 7: 512 cycles  
 */
#define LL_ADKEY_CR_ADC_TRG_SHIFT_SAMPLE(n)                   (((n)&0x7) << 19)

/*! RW, ADC scan channel order
 * The sequence of scan channels is set in a single - cycle scan or continuous scan direction mode  
 * 0: ADC channel selection registers are scanned in order from low to high  
 * 1: ADC channel selection registers are scanned in order from high to low  
 */
#define LL_ADKEY_CR_ADC_SCAN_DIR(n)                           (((n)&0x1) << 16)

/*! RW, Data alignment  
 * 0: right justify  
 * 1: left alignment  
 */
#define LL_ADKEY_CR_ADC_ALIGN(n)                              (((n)&0x1) << 11)

/*! RW, A/D conversion mode (ADC mode) 
 * When changing the conversion mode, the software first disables the ADST bit  
 * 00: single conversion  
 * 01: single cycle scan  
 * 10: continuous scanning  
 */
#define LL_ADKEY_CR_ADC_MD(n)                                 (((n)&0x3) << 9)

/*! RW, A/D conversion start (ADC start)  
 * There are two ways of placing ADST:  
 * 1.In single mode or single cycle mode, after the conversion, ADST will be automatically cleared by the hardware.  
 * 2.In continuous scan mode, A/D conversion will continue until the software writes 0 to the bit or the system reset.  
 * 1 = start of conversion  
 * 0 = end of transition or enter idle state  
 */
#define LL_ADKEY_CR_ADC_ST_EN                                 (1UL << 8)

/*! RW, External trigger source selection  
 * 00: timer0 trigger  
 * 01: timer1 trigger  
 * 02: timer2 trigger  
 * 03: timer3 trigger  
 * 04: timer4 trigger  
 * 05: timer5 trigger  
 * 13: PB7 trigger  
 * 14: PB6 trigger  
 * 15: PC8 trigger  
 * other: reserved  
 */
#define LL_ADKEY_CR_ADC_TRG_SEL(n)                            (((n)&0xF) << 4)

/*! RW, Direct memory access enable  
 * 1 = DMA request enabled  
 * 0 = DMA disabled  
 */
#define LL_ADKEY_CR_ADC_DMA_EN                                (1UL << 3)

/*! RW, External trigger enable  
 * 1 = start A/D conversion using an external trigger signal  
 * 0 = start A/D conversion without an external trigger signal  
 */
#define LL_ADKEY_CR_ADC_EXT_TRG_EN                            (1UL << 2)

/*! RW, A/D interrupt enable  
 * If ADINT is set, an interrupt request is generated at the end of A/D conversion  
 * 1 = enable A/D to be interrupted  
 * 0 = disable A/D interrup  
 */
#define LL_ADKEY_CR_ADC_IE                                    (1UL << 0)

/***** ADKEY_CHS Register *****/
/*! RW, In continuous scan mode, ADC input channel is enabled  
 * 1 = enabled  
 * 0 = disable  
 * CHxEN [0]  : PC0  
 * CHxEN [1]  : PC1  
 * CHxEN [2]  : PC2  
 * CHxEN [3]  : PC3  
 * CHxEN [4]  : PC6  
 * CHxEN [5]  : PC7  
 * CHxEN [6]  : PB14  
 * CHxEN [7]  : PB12  
 * CHxEN [8]  : PB10  
 * CHxEN [9]  : PB8  
 * CHxEN [10] : PB6  
 * CHxEN [11] : PB4  
 * CHxEN [12] : PB2  
 * CHxEN [13] : PB0  
 * CHxEN [14] : PA11  
 * CHxEN [15] : PA10  
 * CHxEN [16] : PA9  
 * CHxEN [17] : PA8  
 * CHxEN [18] : PA7  
 * CHxEN [19] : PA6  
 * CHxEN [20] : PA5  
 * CHxEN [21] : PA4  
 * CHxEN [22] : PA3  
 * CHxEN [23] : PA2  
 * CHxEN [24] : PA1  
 * CHxEN [25] : PA0  
 * CHxEN [26] : BG  
 * CHxEN [27] : temperature  
 * CHxEN [28] : DAC voltage /4  
 * CHxEN [29] : DAC voltage  
 * CHxEN [30] : OPMA  
 * CHxEN [31] : OPMB  
 */
#define LL_ADC_CHS_ADC_EN(n)                              (((n)&0xFFFFFFFF) << 0)

/*! ADC input channel is PC0 */
#define LL_ADC_CHS_PC0                                    (1U << 0)

/*! ADC input channel is PC1 */
#define LL_ADC_CHS_PC1                                    (1U << 1)

/*! ADC input channel is PC2 */
#define LL_ADC_CHS_PC2                                    (1U << 2)
                                                            
/*! ADC input channel is PC3 */                             
#define LL_ADC_CHS_PC3                                    (1U << 3)
                                                            
/*! ADC input channel is PC6 */                             
#define LL_ADC_CHS_PC6                                    (1U << 4)
                                                            
/*! ADC input channel is PC7 */                             
#define LL_ADC_CHS_PC7                                    (1U << 5)

#if defined(__CHIP_PB_NO_REMAP)
/*! ADC input channel is PB14 */                            
#define LL_ADC_CHS_PB14                                   (1U << 6)
                                                            
/*! ADC input channel is PB12 */                            
#define LL_ADC_CHS_PB12                                   (1U << 7)
                                                            
/*! ADC input channel is PB10 */                            
#define LL_ADC_CHS_PB10                                   (1U << 8)
                                                            
/*! ADC input channel is PB8 */                             
#define LL_ADC_CHS_PB8                                    (1U << 9)
                                                            
/*! ADC input channel is PB6 */                             
#define LL_ADC_CHS_PB6                                    (1U << 10)
                                                            
/*! ADC input channel is PB4 */                             
#define LL_ADC_CHS_PB4                                    (1U << 11)
                                                            
/*! ADC input channel is PB2 */                             
#define LL_ADC_CHS_PB2                                    (1U << 12)
                                                            
/*! ADC input channel is PB0 */                             
#define LL_ADC_CHS_PB0                                    (1U << 13)

#else
/*! ADC input channel is PB7 */                            
#define LL_ADC_CHS_PB7                                    (1U << 6)
                                                            
/*! ADC input channel is PB6 */                            
#define LL_ADC_CHS_PB6                                    (1U << 7)
                                                            
/*! ADC input channel is PB5 */                            
#define LL_ADC_CHS_PB5                                    (1U << 8)
                                                            
/*! ADC input channel is PB4 */                             
#define LL_ADC_CHS_PB4                                    (1U << 9)
                                                            
/*! ADC input channel is PB3 */                             
#define LL_ADC_CHS_PB3                                    (1U << 10)
                                                            
/*! ADC input channel is PB2 */                             
#define LL_ADC_CHS_PB2                                    (1U << 11)
                                                            
/*! ADC input channel is PB1 */                             
#define LL_ADC_CHS_PB1                                    (1U << 12)
                                                            
/*! ADC input channel is PB0 */                             
#define LL_ADC_CHS_PB0                                    (1U << 13)
#endif

/*! ADC input channel is PA11 */                            
#define LL_ADC_CHS_PA11                                   (1U << 14)
                                                            
/*! ADC input channel is PA10 */                            
#define LL_ADC_CHS_PA10                                   (1U << 15)
                                                            
/*! ADC input channel is PA9 */                             
#define LL_ADC_CHS_PA9                                    (1U << 16)
                                                            
/*! ADC input channel is PA8 */                             
#define LL_ADC_CHS_PA8                                    (1U << 17)
                                                            
/*! ADC input channel is PA7 */                             
#define LL_ADC_CHS_PA7                                    (1U << 18)
                                                            
/*! ADC input channel is PA6 */                             
#define LL_ADC_CHS_PA6                                    (1U << 19)
                                                            
/*! ADC input channel is PA5 */                             
#define LL_ADC_CHS_PA5                                    (1U << 20)
                                                            
/*! ADC input channel is PA4 */                             
#define LL_ADC_CHS_PA4                                    (1U << 21)
                                                            
/*! ADC input channel is PA3 */                             
#define LL_ADC_CHS_PA3                                    (1U << 22)
                                                            
/*! ADC input channel is PA2 */                             
#define LL_ADC_CHS_PA2                                    (1U << 23)
                                                            
/*! ADC input channel is PA1 */                             
#define LL_ADC_CHS_PA1                                    (1U << 24)
                                                            
/*! ADC input channel is PA0 */                             
#define LL_ADC_CHS_PA0                                    (1U << 25)
                                                            
/*! ADC input channel is PBG */                             
#define LL_ADC_CHS_PBG                                    (1U << 26)
                                                            
/*! ADC input channel is TEMP */                            
#define LL_ADC_CHS_TEMP                                   (1U << 27)
                                                            
/*! ADC input channel is DAC_Voltage/4 */                   
#define LL_ADC_CHS_DAC_V_div_4                            (1U << 28)
                                                            
/*! ADC input channel is DAC_Voltage */                     
#define LL_ADC_CHS_DAC_V                                  (1U << 29)
                                                            
/*! ADC input channel is OPMA */                            
#define LL_ADC_CHS_OPMA                                   (1U << 30)
                                                            
/*! ADC input channel is VSS */                            
#define LL_ADC_CHS_VSS                                    (1U << 31)

/***** ADKEY_STA Register *****/
/*! RW, Current conversion channel  
 * When bit of BUSY is set 1, The six bits represent the channels in the transformation when BUSY = 1  
 * When bit of BUSY is set 0, The six bits represent the channels that can be converted next time  
 */
#define LL_ADKEY_STA_ADC_ONCE_MD_CH_SEL(n)                 (((n)&0x3F) << 4)
/*! RW, The A/D transition state(busy or idle)  
 * 0 = A/D converter is idle  
 * 1 = A/D converter is busy  
 */
#define LL_ADKEY_STA_ADC_BUSY                               (1UL << 2)
/*! RW, A/D Converts the end flag bit(write 1 to clear operation)  
 * This bit is set by the hardware at the end of the channel group conversion and cleared by the software  
 * 1 = A/D conversion is completed  
 * 0 = A/D conversion is incomplete  
 */
#define LL_ADKEY_STA_ADC_DONE_PENDING                       (1UL << 0)

/***** ADKEY_DMAADR Register *****/
/*! RW, DMA start address.
 */
#define LL_ADKEY_DMAADR_ADC_SET(n)                          (((n)&0xFFFFFFFF) << 0)

/***** ADKEY_ADDATA Register *****/
/*! RO, Valid flag  
 * 1 = DATA[11:0] bit DATA is valid  
 * 0 = DATA[11:0] bit DATA is invalid  
 * After the corresponding analog channel conversion is completed, this bit is set 1.  
 * The location bit is cleared by the hardware after reading the ADDATA register.  
 */
#define LL_ADKEY_ADDATA_ADC_VALID_IF_GET(p_adc)            (((p_adc->ADDATA)>>23) & 0x1)
/*! RO, Get data coverage flag  
 * 1 = DATA [11:0] DATA is overwritten  
 * 0 = DATA [11:0] DATA last conversion result  
 * Before the new transformation result is loaded into the register, if the DATA of DATA[15:0] is not read, the OVERRUN will set '1'  
 * After reading the ADDATA register, the bit is cleared by the hardware.  
 */
#define LL_ADKEY_ADDATA_ADC_OVERRUN_IF_GET(p_adc)          (((p_adc->ADDATA)>>22) & 0x1)
/*! RO, The 5 bits show the Channel selection corresponding to the current data  
 */
#define LL_ADKEY_ADDATA_ADC_CH_SEL_GET(p_adc)              (((p_adc->ADDATA)>>16) & 0x3F)
/*! RO, get 12 bit A/D conversion result
 */
#define LL_ADKEY_ADDATA_ADC_RESULT_GET(p_adc)              (((p_adc->ADDATA)>>0) & 0xFFF)

/***** ADKEY_DADAT Register *****/
/*! RW, DAC1(12 bit DAC) data
 */
#define LL_ADKEY_DADAT_DAC_DAT(n)                          (((n)&0xFFF) << 0)

/***** ADKEY_DATCNT Register *****/
/*! RW, The length of data that has been dma completed
 */
#define LL_ADKEY_DATCNT_DMA_DAT_CNT(n)                     (((n)&0x3FF) << 0)

/***** DAC_CON Register *****/
/*! RW, DAC0 Converter enabled
 */
#define LL_DAC_CON_LOCK                                    (1UL<<31)
                                                           
/*! RW, DAC0(6 bit DAC) Converter enabled                
 */                                                        
#define LL_DAC_CON_EN                                      (1UL << 0)
                                                           
/*! RW(reserved), DAC0 vcc /4 is enable                  
*/                                                         
#define LL_DAC_DIV_EN                                      (1UL << 1)
                                                           
/*! RW, DAC0(6 bit DAC) data                             
 */                                                        
#define LL_DAC_CON_DAT(n)                                  (((n)&0x3F) << 2)


/**
  * @}
  */

/** @defgroup ADKEY_LL_Exported_Constants ADKEY LL Exported Constants
  * @ingroup  ADKEY_LL_Driver
  * @brief    ADKEY LL external constant definition
  *
@verbatim   
  ===============================================================================
                                Exported Constants
  ===============================================================================  
  
    Exported Constants mainly restricts the partial configuration of the abstraction 
    layer by using the form of enumeration to facilitate the use and understanding of 
    the module configuration. For the specific enumeration meaning, please refer to 
    the annotation of each module.

@endverbatim
  *
  * @{
  */
  
/***** DRIVER API *****/



/***** LL API *****/



/**
  * @brief Enumeration constant for the clock cycle with a delay of N PCLK starts sampling again
  */
typedef enum {
    /*! Delay 0 PCLK clock cycles before sampling
     */
    LL_ADC_DELAY_NONE = 0,
    /*! Delay 4 PCLK clock cycles before sampling
     */
    LL_ADC_DELAY_4CYCLE,
    /*! Delay 16 PCLK clock cycles before sampling
     */
    LL_ADC_DELAY_16CYCLE,
    /*! Delay 32 PCLK clock cycles before sampling
     */
    LL_ADC_DELAY_32CYCLE,
    /*! Delay 64 PCLK clock cycles before sampling
     */
    LL_ADC_DELAY_64CYCLE,
    /*! Delay 128 PCLK clock cycles before sampling
     */
    LL_ADC_DELAY_128CYCLE,
    /*! Delay 256 PCLK clock cycles before sampling
     */
    LL_ADC_DELAY_256CYCLE,
    /*! Delay 512 PCLK clock cycles before sampling
     */
    LL_ADC_DELAY_512CYCLE,
} TYPE_ENUM_LL_ADC_DELAY;

/**
  * @brief Enumeration constant for low layer ADC scan direction
  */
typedef enum {
    /*! ADC data scan bit is from high to low
     */
    LL_ADC_SCAN_DIR_L2H = 0,
    /*! ADC data scan bit is from low to high
     */
    LL_ADC_SCAN_DIR_H2L,
} TYPE_ENUM_LL_ADC_SCAN_DIR;

/**
  * @brief Enumeration constant for low layer ADC data align mode
  */
typedef enum {
    /*! ADC data is right align
     */
    LL_ADC_DATA_LEFT_ALIGN = 0,
    /*! ADC data is left align
     */
    LL_ADC_DATA_RIGHT_ALIGN,
} TYPE_ENUM_LL_ADC_DATA_ALIGN;

/**
  * @brief Enumeration constant for low layer ADC scan mode
  */
typedef enum {
    /*! ADC scanning mode is single mode
     */
    LL_ADC_MODE_ONCE = 0,
    /*! ADC scanning mode is single cycle mode
     */
    LL_ADC_MODE_SINGLE_CYCLE,
    /*! ADC scanning mode is continuous mode
     */
    LL_ADC_MODE_CONTINUOUS,
} TYPE_ENUM_LL_ADC_SCAN_MODE;

/**
  * @brief Enumeration constant for low layer ADC trigger source selection
  */
typedef enum {
    /*! ADC select time0 trigger mode
     */
    LL_ADC_TRG_SRC_TIME0 = 0,
    /*! ADC select time1 trigger mode
     */
    LL_ADC_TRG_SRC_TIME1,
    /*! ADC select time2 trigger mode
     */
    LL_ADC_TRG_SRC_TIME2,
    /*! ADC select time3 trigger mode
     */
    LL_ADC_TRG_SRC_TIME3,
    /*! ADC select time4 trigger mode
     */
    LL_ADC_TRG_SRC_TIME4,
    /*! ADC select time5 trigger mode
     */
    LL_ADC_TRG_SRC_TIME5,
    /*! ADC select PB7 trigger mode
     */
    LL_ADC_TRG_SRC_PB7 = 13,
    /*! ADC select PB6 trigger mode
     */
    LL_ADC_TRG_SRC_PB6,
    /*! ADC select PC3 trigger mode
     */
    LL_ADC_TRG_SRC_PC3,
} TYPE_ENUM_LL_ADC_TRG_SRC_SEL;

/**
  * @brief comparator0 negative polarity selection mode enum type, consistent with the spec definition.
  */
typedef enum {
    /*! Comparator1 negative input selection is PC0
     */
    LL_ADC_ONCE_MD_CH_SEL_PC0                = 0,
    /*! Comparator1 negative input selection is PC1
     */
    LL_ADC_ONCE_MD_CH_SEL_PC1                = 1,
    /*! Comparator1 negative input selection is PC2
     */   
    LL_ADC_ONCE_MD_CH_SEL_PC2                = 2,
    /*! Comparator1 negative input selection is PC3
     */   
    LL_ADC_ONCE_MD_CH_SEL_PC3                = 3,
    /*! Comparator1 negative input selection is PC6
     */
    LL_ADC_ONCE_MD_CH_SEL_PC6                = 4,
    /*! Comparator1 negative input selection is PC7
     */
    LL_ADC_ONCE_MD_CH_SEL_PC7                = 5,
    #if defined(__CHIP_PB_NO_REMAP)    
    /*! Comparator1 negative input selection is PB14
     */
    LL_ADC_ONCE_MD_CH_SEL_PB14               = 6,
    /*! Comparator1 negative input selection is PB12
     */
    LL_ADC_ONCE_MD_CH_SEL_PB12               = 7,
    /*! Comparator1 negative input selection is PB10
     */
    LL_ADC_ONCE_MD_CH_SEL_PB10               = 8,
    /*! Comparator1 negative input selection is PB8
     */
    LL_ADC_ONCE_MD_CH_SEL_PB8                = 9,
    /*! Comparator1 negative input selection is PB6
     */
    LL_ADC_ONCE_MD_CH_SEL_PB6                = 10,
    /*! Comparator1 negative input selection is PB4
     */
    LL_ADC_ONCE_MD_CH_SEL_PB4                = 11,
    /*! Comparator1 negative input selection is PB2
     */
    LL_ADC_ONCE_MD_CH_SEL_PB2                = 12,
    /*! Comparator1 negative input selection is PB0
     */
    LL_ADC_ONCE_MD_CH_SEL_PB0                = 13,
    #else
    /*! Comparator1 negative input selection is PB7
     */
    LL_ADC_ONCE_MD_CH_SEL_PB7               = 6,
    /*! Comparator1 negative input selection is PB6
     */
    LL_ADC_ONCE_MD_CH_SEL_PB6               = 7,
    /*! Comparator1 negative input selection is PB5
     */
    LL_ADC_ONCE_MD_CH_SEL_PB5               = 8,
    /*! Comparator1 negative input selection is PB4
     */
    LL_ADC_ONCE_MD_CH_SEL_PB4                = 9,
    /*! Comparator1 negative input selection is PB3
     */
    LL_ADC_ONCE_MD_CH_SEL_PB3                = 10,
    /*! Comparator1 negative input selection is PB2
     */
    LL_ADC_ONCE_MD_CH_SEL_PB2                = 11,
    /*! Comparator1 negative input selection is PB1
     */
    LL_ADC_ONCE_MD_CH_SEL_PB1                = 12,
    /*! Comparator1 negative input selection is PB0
     */
    LL_ADC_ONCE_MD_CH_SEL_PB0                = 13,
    #endif
	
	/*! Comparator1 negative input selection is PA11
     */
    LL_ADC_ONCE_MD_CH_SEL_PA11               = 14,
    /*! Comparator1 negative input selection is PA10
     */
    LL_ADC_ONCE_MD_CH_SEL_PA10               = 15,
    /*! Comparator1 negative input selection is PA9
     */
    LL_ADC_ONCE_MD_CH_SEL_PA9                = 16,
    /*! Comparator1 negative input selection is PA8
     */
    LL_ADC_ONCE_MD_CH_SEL_PA8                = 17,
    /*! Comparator1 negative input selection is PA7
     */
    LL_ADC_ONCE_MD_CH_SEL_PA7                = 18,
    /*! Comparator1 negative input selection is PA6
     */
    LL_ADC_ONCE_MD_CH_SEL_PA6                = 19,
    /*! Comparator1 negative input selection is PA5
     */
    LL_ADC_ONCE_MD_CH_SEL_PA5                = 20,
    /*! Comparator1 negative input selection is PA4
     */
    LL_ADC_ONCE_MD_CH_SEL_PA4                = 21,
    /*! Comparator1 negative input selection is PA3
     */
    LL_ADC_ONCE_MD_CH_SEL_PA3                = 22,
    /*! Comparator1 negative input selection is PA2
     */
    LL_ADC_ONCE_MD_CH_SEL_PA2                = 23,
    /*! Comparator1 negative input selection is PA1
     */
    LL_ADC_ONCE_MD_CH_SEL_PA1                = 24,
    /*! Comparator1 negative input selection is PA0
     */
    LL_ADC_ONCE_MD_CH_SEL_PA0                = 25,
    /*! Comparator1 negative input selection is BG
     */
    LL_ADC_ONCE_MD_CH_SEL_BG                 = 26,
    /*! Comparator1 negative input selection is TEMP
     */
    LL_ADC_ONCE_MD_CH_SEL_TEMP               = 27,
    /*! Comparator1 negative input selection is DAC voltage /4
     */
    LL_ADC_ONCE_MD_CH_SEL_DAC_DIV_4          = 28,
    /*! Comparator1 negative input selection is DAC voltage
     */
    LL_ADC_ONCE_MD_CH_SEL_DAC                = 29,
    /*! Comparator1 negative input selection is OPMA
     */
    LL_ADC_ONCE_MD_CH_SEL_OPMA               = 30,
    /*! Comparator1 negative input selection is OPMB
     */
    LL_ADC_ONCE_MD_CH_SEL_OPMB               = 31,
} TYPE_ENUM_LL_ADC_ONCE_MD_CH_SEL;


/***** LL API AND DRIVER API *****/



/**
  * @}
  */

/** @defgroup ADKEY_LL_Exported_Struct ADKEY LL Exported Struct
  * @ingroup  ADKEY_LL_Driver
  * @brief    ADKEY LL external configuration structure definition
  *
@verbatim   
  ===============================================================================
                                Exported Struct
  ===============================================================================  

    Exported Struct mainly extracts the ADC registers from the API, and abstracts 
    the structure. As long as it implements the low coupling between the registers 
    and the registers, the user only needs to configure the structure of the abstraction 
    layer and call hal_adc_init. Function, you can configure the ADC module without 
    involving the configuration of the collective register.

@endverbatim
  *
  * @{
  */

/**
  * @brief Low layer ADC Configure the timer structure for once sample
  */
typedef struct __ll_adc_once_sample_init { 
    /* adc enable             */
    FunctionalState                  adc_en;
    /* adc data align         */
    TYPE_ENUM_LL_ADC_DATA_ALIGN      data_align;
    /* adc channel selection  */
    TYPE_ENUM_LL_ADC_ONCE_MD_CH_SEL  adc_channel;
    /* adc prescaler value    */
    u8                               adc_psc;
} TYPE_LL_ADC_ONCE_SAMPLE_INIT;

/**
  * @brief Low layer ADC Configure the timer structure for single cycle sample
  */
typedef struct __ll_adc_single_cycle_init { 
    /* adc enable */
    FunctionalState                  adc_en;
    /* adc prescaler value */
    u8                               adc_psc;
    /* Interval time period between two consecutive samples (n*ADCCLK) */
    u8                               d2dcyc;
    /* adc data align */
    TYPE_ENUM_LL_ADC_DATA_ALIGN      data_align;
    /* adc channel selection */
    u32                              adc_channel_map;
    /* adc scan direction */
    TYPE_ENUM_LL_ADC_SCAN_DIR        adc_scan_direction;
    /* adc dma enable */
    FunctionalState                  adc_dma_en;
    /* adc dma buff addr */
    u32                              adc_dma_addr;
    
} TYPE_LL_ADC_SINGLE_CYCLE_INIT;

/**
  * @brief Low layer ADC Configure the timer structure for once sample
  */
typedef struct __ll_adc_continus_init { 
    /* adc enable */
    FunctionalState                  adc_en;
    /* adc prescaler value */
    u8                               adc_psc;
    /* Interval time period between two consecutive samples (n*ADCCLK) */
    u8                               d2dcyc;
    /* adc data align */
    TYPE_ENUM_LL_ADC_DATA_ALIGN      data_align;
    /* adc channel selection */
    u32                              adc_channel_map;
    /* adc scan direction */
    TYPE_ENUM_LL_ADC_SCAN_DIR        adc_scan_direction;
    /* adc dma enable */
    FunctionalState                  adc_dma_en;
    /* adc dma buff addr */
    u32                              adc_dma_addr;
    
} TYPE_LL_ADC_CONTINUOUS_CYCLE_INIT;

/**
  * @}
  */

/** @defgroup ADC_LL_Interrupt ADC LL Interrupt Handle function
  * @brief   ADC LL Interrupt Handle function
  *
@verbatim   
  ===============================================================================
                        Interrupt Handle function
  ===============================================================================  

    This subsection provides a set of functions allowing to manage the ADC  
    Interrupt Handle function.

    how to use?

    The ADC interrupt handler uses a callback method that reserves the interface 
    to the user in the form of a callback function. The client needs to initialize 
    the callback function when initializing the ADC in order for the interrupt to 
    be processed normally. 
   
@endverbatim
  *
  * @{
  */



/**
  * @}
  */
  
/** @defgroup ADKEY_LL_Inti_Cfg ADKEY LL Initialization And Configuration
  * @brief    ADKEY LL Initialization And Configuration
  *
@verbatim   
  ===============================================================================
                        Initialization And Configuration
  ===============================================================================  

    This subsection provides a set of functions allowing to manage the ADKEY data 
    Initialization and Configuration.
    
    how to use?

@endverbatim
  *
  * @{
  */

/**
  * @brief  Low layer adc init function
  * @param  p_adc: ponit of adkey
  * @param  p_init : Configure the p_timer initialization structure
  * @retval None
  */
void ll_adc_once_sample_init(ADKEY_TypeDef *p_adc, TYPE_LL_ADC_ONCE_SAMPLE_INIT *p_init);

/**
  * @brief  Low layer adc single cycle mode init function
  * @param  p_adc: ponit of adkey
  * @param  p_init : Configure the adc initialization structure
  * @retval None
  */
void ll_adc_single_cycle_init(ADKEY_TypeDef *p_adc, TYPE_LL_ADC_SINGLE_CYCLE_INIT *p_init);

/**
  * @brief  Low layer adc continuous mode init function
  * @param  p_adc: ponit of adkey
  * @param  p_init : Configure the adc initialization structure
  * @retval None
  */
void ll_adc_continuous_cycle_init(ADKEY_TypeDef *p_adc, TYPE_LL_ADC_CONTINUOUS_CYCLE_INIT *p_init);

/**
  * @brief  Low layer dac0 start function
  * @param  None
  * @retval None
  */
void ll_dac0_set_data(u8 data);

/**
  * @brief  Low layer adc1 start function
  * @param  None
  * @retval None
  */
void ll_dac1_set_data(u16 data);


/**
  * @}
  */
  
/** @defgroup ADKEY_LL_Data_Transfers ADKEY LL Data transfers functions
  * @brief    ADKEY LL Data transfers functions 
  *
@verbatim   
  ===============================================================================
                            Data transfers functions
  ===============================================================================  

    This subsection provides a set of functions allowing to manage the ADKEY data 
    transfers and receive.
  
@endverbatim
  *
  * @{
  */

/**
  * @brief  Low layer adc interrupt enable function
  * @param  None
  * @retval None
  */
void ll_adc_interrupt_enable(void);

/**
  * @brief  Low layer adc interrupt disable function
  * @param  None
  * @retval None
  */
void ll_adc_interrupt_disable(void);

/**
  * @brief  Low layer adc interrupt get function
  * @param  None
  * @retval result
  */
#define LL_ADC_INTERRUPT_GET()                         (ADKEY->CR & LL_ADKEY_CR_ADC_IE)

/**
  * @brief  Low layer adc over run interrupt enable function
  * @param  None
  * @retval None
  */
void ll_adc_ovr_interrupt_enable(void);

/**
  * @brief  Low layer adc over run interrupt disable function
  * @param  None
  * @retval None
  */
void ll_adc_ovr_interrupt_disable(void);

/**
  * @brief  Low layer adc over run interrupt get function
  * @param  None
  * @retval result
  */
#define LL_ADC_OVR_INTERRUPT_GET()                     (ADKEY->CR & LL_ADKEY_CR_ADC_OVR_IE)

/**
  * @brief  Low layer adc enable function
  * @param  None
  * @retval None
  */
void ll_adc_enable(void);
/**
  * @brief  Low layer adc disable function
  * @param  None
  * @retval None
  */
void ll_adc_disable(void);

/**
  * @brief  Low layer adc enable get
  * @param  None
  * @retval result
  */
#define LL_ADC_EN_GET()                   (ADKEY->CFG & LL_ADKEY_CFG_ADC_EN)

/**
  * @brief  Low layer adc dma enable function
  * @param  None
  * @retval None
  */
void ll_adc_dma_enable(void);
/**
  * @brief  Low layer adc dma disable function
  * @param  None
  * @retval None
  */
void ll_adc_dma_disable(void);

/**
  * @brief  Low layer adc dma enable get
  * @param  None
  * @retval result
  */
#define LL_ADC_DMA_EN_GET()             (ADKEY->CR & LL_ADKEY_CR_ADC_DMA_EN)

/**
  * @brief  Low layer adc external interrupt source enable function
  * @param  None
  * @retval None
  */
void ll_adc_ext_trg_src_enable(void);
/**
  * @brief  Low layer adc external interrupt source disable function
  * @param  None
  * @retval None
  */
void ll_adc_ext_trg_src_disable(void);

/**
  * @brief  Low layer adc external interrupt source enable get
  * @param  None
  * @retval result
  */
#define LL_ADC_EXT_TRG_SRC_EN_GET()          (ADKEY->CR & LL_ADKEY_CR_ADC_EXT_TRG_EN)

/**
  * @brief  Low layer adc start enable function
  * @param  None
  * @retval None
  */
void ll_adc_start_enable(void);
/**
  * @brief  Low layer adc start disable function
  * @param  None
  * @retval None
  */
void ll_adc_start_disable(void);

/**
  * @brief  Low layer adc start enable get
  * @param  None
  * @retval result
  */
#define LL_ADC_START_EN_GET()                          (ADKEY->CR & LL_ADKEY_CR_ADC_ST_EN)
/**
  * @brief  Low layer adc done pending get function
  * @param  None
  * @retval value
  */
#define LL_ADC_DONE_PENDING_GET()                      (ADKEY->STA & LL_ADKEY_STA_ADC_DONE_PENDING)
/**
  * @brief  Low layer adc done pending clear function
  * @param  None
  * @retval None
  */
#define LL_ADC_DONE_PENDING_CLR()                      (ADKEY->STA |= LL_ADKEY_STA_ADC_DONE_PENDING)


/**
  * @brief  Low layer adc0 enable function
  * @param  None
  * @retval None
  */
void ll_dac0_enable(void);
/**
  * @brief  Low layer adc1 enable function
  * @param  None
  * @retval None
  */
void ll_dac1_enable(void);

/**
  * @brief  Low layer adc0 enable function
  * @param  None
  * @retval None
  */
void ll_dac0_disable(void);
/**
  * @brief  Low layer adc1 enable function
  * @param  None
  * @retval None
  */
void ll_dac1_disable(void);

/**
  * @brief  Low layer adc0 enable get
  * @param  None
  * @retval result
  */
#define LL_DAC0_EN_GET()                               (DAC->CON & LL_DAC_CON_EN)
/**
  * @brief  Low layer adc1 enable get
  * @param  None
  * @retval result
  */
#define LL_DAC1_EN_GET()                               (ADKEY->CFG & LL_ADKEY_CFG_ADC_EN)


/**
  * @}
  */

/**
  * @}
  */

#ifdef __cplusplus
}
#endif

/**
  * @}
  */

/**
  * @}
  */

#endif //__TS32FX_LL_ADKEY_H

/*************************** (C) COPYRIGHT 2018 TOPSYS ***** END OF FILE *****/
